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Symbian Authors: Jack Newton, Kevin Benedict, Matthew Lobas, Shelly Palmer, RealWire News Distribution

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Research and Markets: Reverse Costing Report of the VGA Camera Module Supplied by ST Microelectronics

Research and Markets (http://www.researchandmarkets.com/research/7xtptx/stmicro) has announced the addition of the "STMicro Wafer-Level Camera - WLP CIS + Heptagon WL-Optic Reverse Costing" report to their offering.

System Plus Consulting is proud to publish the reverse costing report of the VGA Camera Module supplied by ST Microelectronics for the Nokia 2330 mobile phone. This camera module integrates an 2.2µm pixel CMOS Image Sensor (CIS) from STMicro. The CIS die is manufactured using a CMOS technology with a 0.18µm process. The CIS is Wafer-Level Packaged (WLP) using a TSV "via last" technology. The optical module comes from Heptagon and is manufactured with a wafer-level approach.

- Physical Analysis of the Camera and the CMOS Image Sensor

- Step by Step Reconstruction of the Process Flow

- Cost of Manufacturing and Estimation of Selling Price

This report provides complete teardown of the camera module with:

- Detailed photos

- Material analysis

- Schematic assembly description

- Manufacturing Process Flow

- In-depth economical analysis

- Manufacturing cost breakdown

- Selling price estimation

Key Topics Covered:

Glossary

Overview/Introduction

- Executive Summary

- Reverse Costing Methodology

Companies Profiles

- CMOS Image Sensors. Volume Shipments

- STMicroelectronics Profile

- Heptagon Profile

Nokia 2330 Teardown

Physical Analysis

- Camera Module Views & Dimensions

- Camera X-Ray

- Camera Module Disassembly

- CIS Views & Dimensions

- CIS Markings

- CIS Bonding

- CIS Microlenses

- CIS Pixels

- CIS Back view

- Camera Module Cross-section

- Package Cross-section

- Optical Module Cross-section

- CIS Packaging Cross-section

- CIS Cross-section

Manufacturing Process Flow

- CIS Process Flow

- CIS Wafer-level packaging Process Flow

- Description of the CIS Wafer Fabrication Unit

- WL-Optic Process Flow

- Description of the WL-Optic Wafer Fabrication Unit

Cost Analysis

- CIS FEOL + BEOL Cost

- CIS Front-End Cost

- CIS Back-End 0 : 1st Probe Test & Optical Test

- CIS WLP Cost

- CIS WLP Cost per Process Steps

- CIS WLP : Equipment Cost per Family

- CIS WLP : Material Cost per Family

- CIS Die Cost

- WL-Optic Front-End Cost

- WL-Optic Cost per Process Steps

- WL-Optic : Equipment Cost per Family

- WL-Optic : Material Cost per Family

- WL-Optic : Test, dicing and assembly

- WL-Optic Price

- Back-End : Final Packaging & Test

- Camera Module Cost (CIS + WLO + Packaging)

Estimated Price Analysis Conclusion

For more information visit http://www.researchandmarkets.com/research/7xtptx/stmicro

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